1. Field of the Invention
The present invention generally relates to electrostatic discharge (ESD) protection. More specifically, the present invention provides ESD protection for high voltage integrated circuits (ICs).
2. Background Art
It is often difficult to provide ESD protection on a high voltage IC that requires devices with high voltage tolerances. High voltage devices must have breakdown voltages that are higher than the operating voltages of the high voltage IC. The ESD protection must provide an ESD trigger voltage that is higher than the operating voltages of the high voltage IC and yet lower than the breakdown voltages of the high voltage devices. The operating voltages of the high voltage IC often approach the breakdown voltages of the high voltage devices, thereby making an acceptable range of the ESD trigger voltage narrow and difficult to achieve.
Conventional IC devices, such as Metal-Oxide Semiconductor (MOS) Field Effect Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs), fail to provide voltage tolerances required by high voltage ICs. High voltage devices are therefore typically constructed with alternative technologies. These alternative high voltage devices may include Lateral Diffused MOS (LDMOS) transistors, Lateral Insulated Gate Bipolar Transistors (LIGBTs) and other devices. Since these high voltage devices are designed to withstand high voltages, they are not optimized to work as ESD discharge devices. Conventional devices cannot be used to provide ESD protection because the operating voltages usually exceed the breakdown voltages of the conventional devices.
Silicon Controlled Rectifier (SCR) structures are commonly used to provide ESD protection for high voltage ICs. A drawback of the SCR device is its relatively slow turn-on time. Another drawback of the SCR device is its triggering mechanism. The triggering of the SCR device is initiated by a substrate current generated by a pn-junction breakdown. This pn-junction, however, is also designed to have a high breakdown voltage for use in high voltage applications. Therefore, it is difficult to design the SCR device with a pn-junction that can satisfy these conflicting design goals. The effectiveness of the SCR structure is further compromised when a low resistively substrate is used, a common practice for high voltage ICs.
Processing steps used to fabricate high voltage ICs also render other commonly used ESD protection techniques ineffective. For example, snapback MOS devices provide poor ESD protection because their desired parasitic bipolar characteristic is purposely subdued in many fabrication processes. MOS-based ESD protection devices suffer from the characteristic high threshold voltage and channel resistance of high voltage MOSs, which results in excessive layout overhead. Diode-based ESD protection devices suffer from the high parasitic series resistance inherent in high voltage processing techniques, which also results in excessive layout overhead. Another obstacle in the design of high voltage ESD protection includes building resistors and capacitors in the ESD protection circuits that can tolerate high voltages.